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TECHNOLOGY TRENDS

Advanced wafer-level packaging offers a

sustainable path to high-performance computing

By Sally-Ann Henry, Jim Straus [ACM Research]
H eterogenous integration techniques [1]. According to Yole to five RDL layers, and a line/space

( H I ) , a k e y t r e n d
Développement, the total WLP market
metric of less than 8µm, with many now
i n s e m i c on d u c t or
development [3].
manufacturing, is becoming will reach $5.5 billion by 2025 [2]. This down to 5µm in production and 2µm in
includes fan-in, FOWLP, 2.5D and
the path to extending Moore’s Law 3D WLPs. It is the latter three that are At around 65nm, copper (Cu) pillars
in terms of power, performance, area impacting the shift in manufacturing replaced traditional wafer bumps to
and cost (PPAC). Advanced wafer- process and tools. enable higher density interconnect
level packaging (WLP) architectures— While there was a brief pause in market between die, or between die and the
including fan-in and fan-out WLP growth, caused by uncertainty when packaging substrate. They are used
(FOWLP), 2.5D and 3D WLPs—are key COVID-19 began, the market quickly mainly in 2.5D and 3D packaging where
enablers of HI. They make it possible recovered and shifted into overdrive TSVs are used and are more complex to
to pack 5G, artificial intelligence (AI), to meet the demands of the digital fabricate than bumps. Cu pillar diameters
memory, power, sensors, and more into transformation. As a result, we are in range from 20µm down to 5µm. At 5µm
the electronic devices the world relies on the midst of a global chip shortage. The diameter and 50µm depth, TSVs are a
every day in more applications than ever. outsourced semiconductor assembly and challenge to plate and fill.
Additionally, the power efficiency of 3D test suppliers (OSATS) have indicated that Many of the processes being used
WLP helps to reduce carbon emissions, they are at capacity for not only WLP, but for advanced WLP are adaptations of
providing a sustainable pathway to all types of semiconductor packages, and those originally developed for front-
high-performance computing (HPC). the only thing that will slow the pace of end wafer processing. One example is
How those 3D WLPs are built in high growth are shortages in the supply chain. using high-density RDL to maximize
volumes also contributes to achieving FOW LP per for ma nce. P rocesses
semiconductor manufacturers’ goals of WLP manufacturing trends used to create RDL patterns include
zero waste to landfills. In this article, we W h i l e t r a d i t i o n a l p a c k a g i n g advanced lithography, deposition, etch,
explore manufacturing processes and architectures—such as lead frame, quad and chemical mechanical planarization
tools used to build WLPs, and what can flat no lead (QFN), wire bond and even (CMP). TSVs require etch and deposition
be done to make them more sustainable. flip chip—begin with die that are diced processes. Wafer bumping and wafer
and ready for assembly, WLP is so called bonding also require CMP process steps.
WLP trends: what is driving growth? because final assembly, packaging and
Not only do WLPs provide the requisite test take place while the die are still in Tools of the trade
design flexibility and thin form factor wafer form. FOWLP deviates slightly In the early days of WLP, as it was
needed to increase the performance of from this, as known-good dies (KGD) are beginning to take hold, the industry saw
today’s data-driven devices and servers, assembled to create a reconstituted wafer the proliferation of new tool suppliers
they also deliver the reduced power that implements a redistribution layer who carved a niche for themselves by
consumption and extended battery life (RDL) to fan out the interconnects from developing WLP process tools targeted
that sustainability-conscious consumers the die to the package, thereby increasing specifically to the OSATS.
expect from their electronics. While WLP the interconnect density.
got its start in mobile devices, advanced Achieving a high-density interconnect These tools included those used for:
FOWLP, 2.5D and 3D WLP using is the driving force in optimizing all • Electrochemical plating (ECP) for
through-silicon via (TSV) interconnects types of WLP. To increase inputs/outputs Cu bump RDL, as well as TSV
are being used in HPC applications (I/Os), RDL layers are added, bump metallization such as barrier, seed
like data centers, gaming, 5G network sizes are reduced, and TSVs must have and fill;
infrastructures, AI, and more. higher aspect ratios. For example, low • CMP for wafer bumping, RDL
According to market analysts, the density FOWLP—such as embedded and hybrid bonding surface
global WLP market size is expected to wafer-level ball grid array (eWLB)— preparation; and
flourish at a compound annual growth have fewer than 500 I/Os, no more than • Wet processing tools used for
rate of 21% between 2021 and 2028, as two RDL layers, and line/space widths of deposition processes such as
WLP continues to establish technical <8µm. Conversely, today’s high-density coating, developing and plating, as
superiority over traditional packaging FOWLPs have more than 500 I/Os, three well as stripping and etching.

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