Page 10 - Chip Scale Review_November December_2021-digital

The importance of sustainable 2. M. LaPedus, “Shortages, challenges
Now that HI and “More than Moore” manufacturing engulf packaging supply chain,”
solutions are seen as the path to PPAC, While semiconductors are at the heart Semiconductor Engineering, Feb,
leading foundries and integrated device of all the smart technologies that promise 18, 2021 https://semiengineering.
manufacturers (IDMs) have shifted R&D to create a more sustainable world, the way com/shortages-challenges-engulf-
focus from traditional scaling to develop we manufacture them is part of the global packaging-supply-chain/
leading-edge chiplet HI architectures problem known as climate change. For 3. M. LaPedus, “Elect roplat i ng
using all the tools in the WLP toolbox. example, fabricating a small 2g microchip IC challenges,” Semiconductor
They are leveraging not only process requires 32kg of water, 1.6kg of petroleum, Eng., Apr il 10, 2017, ht t ps://
know-how, but legacy systems to compete and 72g of chemicals [4]. Multiply this by semiengineering.com/electroplating-
with OSAT providers for WLP business. vast volumes of chips we produce each ic-packages/
This worked well for early iterations year to support the global data explosion 4. “How can the semiconductor
of WLPs built using legacy node chips generated by these innovations, and we are industry achieve sustainability?”
that did not quite need the level of at risk of causing as much harm as good [5]. S e m i c o n d u c t o r Re v i e w ,
precision and cleanliness required for As the semiconductor indust r y O ct. 12 , 2020, ht t p s://w w w.
today’s advanced WLP technologies. endeavors to support technologies that semiconductorreview.com/news/
Additionally, as OSATS couldn’t easily will make the world a better, safer, how- ca n-t he -sem iconduct or-
absorb the cost of front-end tools, systems cleaner place, we need to increase efforts industry-achieve-sustainability--
stripped of all the front-end bells and for sustainability in semiconductor nwid-135.html
whistles made it economically feasible for manufacturing. If we focus on reducing 5. J. Straus, “W hat you need to
OSATS to add capacity for WLP. our environmental footprint, we can make k now about sustainabilit y in
However, as technology nodes continue sure we’re not simultaneously destroying semiconductors,” May 12, 2021,
to shrink, the argument for front-end- the world we are trying to save [6]. https://www.3dincites.com/2021/05/
level tool capability grows. From high- So in addition to optimizing all these what-you-need-to-know-about-
aspect ratio TSVs and finer-bump pitches processes for WLP applications, today’s sustainability-in-semiconductors/
to tighter RDL line/space widths and tools must also be designed to help 6. Ibid.
precision flatness for hybrid bonding, foundries, IDMs and OSATS reach their
tools designed for early generations of zero-waste-to-landfill goals with tools Biographies
WLP are not meeting today’s needs for designed to reduce, reuse and recycle the Sally-A n n Hen r y is a business
higher levels of precision, uniformity chemistries used in wet wafer processing. development leader at ACM Research,
and contamination control. Wafer- Fremont, CA. She is a seasoned
level processes have become much less Summary semiconductor leader, visionary and
forgiving, and call for tools with front- At ACM Research, we’ve leveraged process professional who has deep
end processing capabilities. But these our knowledge and expertise in front- expertise in semiconductor back end
tools must still be affordable to keep end process solutions and adapted them of line product management, planning,
OSATS in the game. Additionally, as to address today’s high-volume WLP q u a l it y s y s t e m s a n d wo rld w id e
WLP products gain market share, all challenges. In addition to addressing ECP customer relationship management.
these processes must be adapted for high- challenges, we have developed a process In her role at the company she excels
volume manufacturing environments. for removing excess copper and the top at working cross-culturally to solve
For example, there’s a need for plating barrier layer from TSVs and Cu pillars semiconductor process issues across
metal films in deep vias or troughs with without inducing mechanical stress. We Europe, Asia, and the United States.
depths more than 200µm at high plating are committed to supporting sustainable Email sallyann.henry@acmrsch.com
rates. The process needs to address the manufacturing efforts. To this end, we’ve Jim Straus is VP of Sales at ACM
mass transfer challenge while achieving developed closed-loop systems that Research, Fremont, CA. He has more than
a better pillar-top profile and delivering require lower chemistry volumes and 30 years of semiconductor manufacturing
improved height uniformity, and better recycle and reuse chemistries in real time equipment industry experience and
uniformity at a higher throughput. to make the processes eco-friendly. has led organizations focused on
The fine features of RDL line and space, providing success for semiconductor
Cu pillar bumps and TSV fabrication rely on References manufacturers of all types, including
advanced wet wafer processes for cleaning, 1. “Global wafer-level packaging global multinational corporations.
coating, developing, photoresist stripping market is expected to grow at a rate
and etching. Hybrid bonding processes such of 21.0% during the anticipated
as direct bond interconnect (DBI) calls for period of 2021 to 2028,” Data Bridge
removing excess copper and the top barrier Market Research https://www.
layer without inducing mechanical stress. databridgemarketresearch.com/news/
It also requires wafers that are particle free, global-wafer-level-packaging-market
with extremely smooth surfaces.

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