Page 61 - Chip Scale Review_November December_2021-digital

implementations each providing scan and receive rates while supporting of a commercially-available processor
access to about 20% of all digital devices. advanced flexible error-capture modes at core that can handle calibration, data
By 2030, SERDES and 1149.10 could the same speeds. embedding, compensation, and related
combine to provide scan access to about Similarly, convergence technology tasks without burdening a dedicated
60% of all digital devices, with classic scan can be leveraged to implement a dual test processor.
finding use in only about 20% of devices. sequencer that can speed up test tasks In addition, an ATE system used to test
At the same time, as device nodes involving matched loops and jumps convergence and exascale devices can be
continue to shrink, power-supply while minimizing test-time overhead, seen as a distributed system with massive
requirements continue to escalate. ATE and it can enable fast and simple timing compute power, posing data aggregation
makers are seeing a demand for more measurements. An ATE system can also and distribution challenges involving
power in general as well as a need to incorporate edge computing in the form the ATE’s system level, card-cage level,
support more power domains and test
integrated power-management ICs
(PMICs), requiring high-performance
and flexible device-power-supply (DPS)
test resources.
In addition, as voltage levels go down,
device power supply (DPS) instruments
must offer better accuracy and better
dynamic performance. For example,
devices require power supplies that can
accommodate fast switching with no
glitches, providing stable and consistent
performance. Today, PMICs already
reside close to the central processing
unit (CPU), and the trend will continue.
The age of convergence will also see
new requirements for high-voltage
test. While 48V levels have been found
primarily in PMIC chips targeting
datacenter equipment, the higher voltages
are beginning to appear on system on
chips’ (SoC) designs as well. In addition,
multisite testing demands will increase,
with the industry looking to keep test costs
in line and to shrink time to market.
In the age of convergence and exascale
computing, test data collection is becoming
critical—the ATE must collect massive
amounts of test data quickly by employing
advanced error-capture modes, and it
must subsequently feed that data back
into electronic design automation (EDA)
tools to help isolate yield-limiting issues
and accelerate yield learning. Yet another
trend involves the increasing levels of radio
frequency (RF) integration into digital
chips, driving requirements for ATE signal
processing units that can perform the
number crunching required for the post-
processing of mixed and RF signal data.
For t u nately, the ATE i ndust r y RoHS
can leverage the same convergence P
and exascale technology trends and
technologies that chip manufacturers
are exploiting to meet emerging test
challenges. For example, a test company
can leverage new technology waves to
build high-performance test processors
that can operate at 5Gbps transmit

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