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A multi-channel system on chip (SoC) virtually. Here, good resolutions are bumps. The potential root cause for such
ATE – an established tool to detect accomplished even for large samples a defect could be due to the bridging
defects in a package – is used to identify by utilizing a two-stage technique: of bumps induced by package warpage
the faulty pin. However, ATE results geometric and optical magnifications during reflow, or a particulate issue.
cannot define the correct location of facilitated by multiple objectives. The developed methodology can be
the failure in a package. Therefore, an In comparison, conventional micro successfully applied to carry out rapid
improved technique called electro-optical computed tomography (micro-CT) nondestructive failure analysis of 2.5D
terahertz pulse reflectometry (EOTPR) employs geometric magnification and as a IC packages by accurately localizing the
is engaged to localize the failure. It is result, the resolution diminishes intensely defects that are internal to the package.
capable of rapidly and nondestructively while processing large samples. He t er og e n e o u s i n t e g r a t io n i s
localizing shorts, leakages, and open Fault localization methodology for increasingly adopted by the industry
failures in different device architectures a through-Si interposer-based 2.5D IC to address current and next-generation
with good localization accuracy. High- package comprising dies assembled pro duct r e qu i r e me nt s. I M E a nd
frequency electrical pulses are injected onto the silicon interposer, which is then Xilinx will continue to collaborate to
into the device under test (DUT) through assembled on the organic substrate, is enhance the reliability performance
a probe, which is contacted to the DUT described in Figure 3. The fault was of next-generation products that use
solder ball using a probe station. A found to be a short defect that could be heterogeneous integration on stacked-
photoconductive switch records the inferred by a distinct low-impedance silicon interposers and in advanced fan-
reflection of the launched signal caused feature from the EOTPR experiment out wafer-level packages.
by structures within the device and (Figure 3b); the location of the defect
faults as a voltage-time waveform. By was identified to be at a C4 bump near Reference
making use of this time-based data, to the substrate surface. Figures 3c 1. “Polymeric Materials for Advanced
faults inside advanced packages are and 3d show the 3D and extracted 2D Packaging at the Wafer-Level,” Yole
localized with minimal references to the images of the short between four C4 Développement, 2018.
internal structure.
To assist and evaluate the defect
localization, a model is created that
employs a one-dimensional lump circuit
model to quickly simulate the measured
data. The simulation enables equivalent
circuits to be defined as elements in
a sequence that may include RLC
impedances and transmission lines
with radiative transmission losses. The
process of creating the model can be
completed in not more than 30 minutes
and the optimized model can be saved for
subsequent usage. The complete defect
localization procedure typically takes
less than 5 minutes while importing a
waveform of a failed sample into a pre-
optimized model. Post-defect localization,
the faults are nondestructively visualized
and confirmed by utilizing a 3-D
X-ray microscopy (XRM) imaging
method. XRM can nondestructively
pass through advanced IC packages
with multiple stacks and image internal
structures with a high resolution of <1μm
without damaging the sample. Besides
the nondestructive capability of this
technique, it does not need any time-
consuming sample preparation steps. As
it offers images of the internal structures
in 3D, it facilitates a detailed study of
failures by providing limitless cross-
sectioning from all preferred angles

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