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Figure 2: TSMC SoIC™ technology.
TSMC proposes its bumpless System to the chiplet ball map using a built-in [5]. Benefits include security and potential
on Integrated Chip (SoIC™) as one chiplet programmable connectivity and power cost reduction.
solution (Figure 2). The SoIC™ is a 3D array. The smart fabric provides field-
structure formed by stacking logic, memory, programmable connectivity and connects I/ Summary
or both chip types on an active interposer Os of various chiplets based on a program C h i ple t s a r e a h e t e r oge n e ou s
with through-silicon vias (TSVs). A chip-on bit stream. Additionally, the smart fabric integration solution that can move us
wafer (CoW) process is used and the process has built-in voltage regulators, power into the next semiconductor era. While
can handle a <10µm bond pad pitch between management circuits, a programmable it is technologically possible to continue
chips. The chips, with or without TSVs, are memory, level shifters, programmable scaling monolithic die, the economics do
bonded onto the wafer containing the active I/O to the outside, and other peripherals. not favor this approach. The use of chiplets
interposers using a hybrid bonding process. The smart fabric is programmable at will become a game changer in the new
The 3D chip with TSV SoIC™ also uses manufacturing time through zGlue’s era for the companies that can master
a through-dielectric via and CoW bond. firmware application program interface. the design of this new approach. New
TSMC reports that the SoIC™ structure Software programmability allows rapid players are emerging that will help others
with its higher density bonding provides configuration for chiplet-based systems on participate in the bold new chiplet era.
better signal integrity, power integrity, and the order of days and weeks. Connection to
lower communication latency with greater RF and sensitive analog signals are handled References
bandwidth than a conventional 3D IC using in the redistribution layer (RDL). The 1. J. Vardaman, “Chiplets: the new era
TSVs and 40µm pitch micro bumps. Lower zGlue integration platform is called (ZiP). begins,” The 3D InCites Yearbook,
insertion loss, important for 5G applications, A unique method of surface tension is used Mar. 2020, pp.13, 55.
is reported. Lower parasitics and low IR to connect the chiplets to the active silicon 2. M. Bhagavat, “Packaging renaissance
drop is reported. Finer interconnect pitch is interposer or smart fabric. Connections with chiplets,” IMAPS Keynote,
possible and there is less concern with chip- with pitch as small as 50µm are possible. IMAPS Conf., Oct. 2019.
package interaction (CPI) because there are Programmability of zGlue bumps also 3. F. Chen, et al., “System on integrated
no bumps [3]. enables some repair and reconfigurability chips (SoIC) for 3D heterogeneous
after manufacturing [4]. integration,” Elec. Comp. and Tech.
zGlue Conf. (ECTC), May 2019, pp. 594-599.
California start-up zGlue offers an online DARPA 4. J. Nasrullah, et al., “Designing
tool, called ChipBuilder, to build chiplets to The Defense Advanced Research Projects software configurable chips and SiPs
connect to its smart silicon interposer that Agency (DARPA) Common Heterogeneous using chiplets and zGlue,” IMAPS
allows the use of third-party chiplets. The Integration and IP Reuse Strategies Inter., Sept. 30–Oct. 3, 2019.
chiplets, fabricated as wafer-level packages (CHIPS) program is focused on creating 5. T. Coughlin, “Chiplets for All,”
(WLPs), can be connected to an active an open interface, including a switch fabric Forbes, May 11, 2019.
silicon interposer called Smart Fabric. The interconnect to connect logic blocks inside
company has created a library of more than devices, to created multi-chip modules Biography
250 off-the-shelf chiplets and plans to extend (MCMs) using chiplets instead of traditional E. Jan Vardaman is President of
it to more than 1,500 in the near future. system on chip (SoC) devices. Breaking the TechSearch International, Inc., Austin,
The active silicon interposer or smart SoC into separate chiplets allows proprietary TX. She received her BA from Mercer
fabric has a fine-pitch Cu pillar micro- operations to be fabricated separately from U., and MA in Economics from the U. of
bump array on the surface that can conform the licensed and tested commodity IP chips Texas. Email jan@techsearchinc.com

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