Page 5 - ChipScale_May-June_2020-digital
P. 5

The Future of Semiconductor Packaging


      STAFF                                                                              Volume 24, Number 3
      Kim Newman Publisher                                                                    May • June 2020
      knewman@chipscalereview.com
      Lawrence Michaels Managing Director/Editor
      lmichaels@chipscalereview.com           FEATURE ARTICLES
      Debra Vogler Senior Technical Editor
      dvogler@chipscalereview.com
                                             20 Testing AiP modules in high-volume
      CONTRIBUTING EDITORS                        production for 5G applications
 ACCELERATING  Steffen Kröhnert - Advanced Packaging  By Jose Moreira
      steffen.kroehnert@espat-consulting.com
                                                  [Advantest]
      John L. Lau, Ph.D - Advanced Packaging
 HETEROGENEOUS  john_lau@unimicron.com       26   Embedded trace and 2-in-1 RDL for fan-out
      Ephraim Suhir, Ph.D - Reliability
      suhire@aol.com
                                                  panel-level packaging
 INTEGRATION  Rao R. Tummala, Ph.D - Advanced Packaging  By Kesheng Feng and Kwangsuk Kim
      rao.tummala@ece.gatech.edu
                                                  [MacDermid Alpha Electronics Solutions]
      EDITORIAL ADVISORS
      Andy Mackie, Ph.D (Chair) - Indium Corporation
      Rolf Aschenbrenner, Dipl.-Phys. - Fraunhofer IZM  31 The true cost of undetected defects
      Arun Gowda, Ph.D - GE Global Research
      John Lau, Ph.D - Unimicron                  By David L. Adler and Brennan Peterson
      Leon Lin Tingyu, Ph.D - National Center for Advanced   [SVXR Inc.]
      Packaging (NCAP China)

      SUBSCRIPTION—INQUIRIES
      Chip Scale Review                      34 AI’s impact on 3D packaging:
      All subscription changes, additions, deletions to any
      and all subscriptions should be made by email only to     heterogeneous integration
      subs@chipscalereview.com                    By Santosh Kumar
                                                  [Yole Développement, Korea]

      Advertising Production Inquiries:
      Lawrence Michaels
      lmichaels@chipscalereview.com          38 Demand for 3D devices drives inspection
                                                  and metrology innovation
 EV Group establishes Heterogeneous Integration Competence Center™ to accelerate  Copyright © 2020 Haley Publishing Inc.  A Q&A with Raj Jammy
      Chip Scale Review (ISSN 1526-1344) is a registered trademark of
                                                  [Carl Zeiss SMT Inc., the North American subsidiary of
 new product development fueled by heterogeneous integration and advanced packaging  Haley Publishing Inc. All rights reserved.  Carl Zeiss SMT GmbH]
      Subscriptions in the U.S. are available without charge to qualified individuals
      in the electronics industry.  In the U.S. subscriptions by first class mail are   39 Rapid analysis of buried 2.5/3D
 Open access innovation incubator for EVG customers and partners across the  $125 per year.  Subscriptions outside of the United States are $225 per year
      to other countries.
 microelectronics supply chain, guaranteeing the highest IP protection standards  Chip Scale Review, (ISSN 1526-1344), is published six times a  package structures
                                                  By Cheryl Hartfield
      year with issues in January-February, March-April, May-June, July-  [ZEISS Semiconductor Manufacturing Technology,
      August, September-October and November-December. Periodical
      postage paid at Los Angeles, Calif., and additional offices.  Process Control Solutions]
 Combining EVG’s world-class wafer bonding, thin-wafer handling and lithography   POSTMASTER: Send address changes to Chip Scale Review magazine
 products and expertise, as well as pilot-line production facilities and services  P.O. Box 2165, Morgan Hill, CA 95038
      Printed in the United States           43 Scaling CMOS beyond FinFETs: from
                                                  nanosheets and forksheets to CFETs
 Leveraging the state-of-the-art cleanroom facilities at EVG’s headquarters in Austria,   By Julien Ryckaert
 supported by EVG’s worldwide network of process technology teams  [imec]


             Official Publication Sponsor



               Official Media Sponsor



 GET IN TOUCH to discuss your manufacturing needs
 HeterogeneousIntegration@EVGroup.com  Co-Host & Organizer
                                                               Chip Scale Review   May  •  June  •  2020   [ChipScaleReview.com]  3 3
   1   2   3   4   5   6   7   8   9   10