Page 9 - Chip Scale Review_July August_2023-digital

EXECUTIVE VIEWPOINT

A new generation of e-beam lithography

to enable packaging at the leading edge

By David K. Lam, Ken MacWilliams [Multibeam Corporation]

A d va n c e d p a c k a g i ng higher bandwidth in package. Indeed, H o w e v e r, i t h a s n e v e r m e t t h e

throughput standards required for
technologies are enabling
demands for larger interposers, more
hardware improvements
fully automated and employs multiple
power, lower latency, and lower power
in artificial intelligence I/O, greater bandwidth, more processing fab production. In contrast, MEBL is
(AI), 5G, high-performance computing usage are converging to drive the need miniature e-beam columns operating
(HPC), smart cars, and other applications for a new generation of lithography in concert to pattern full wafers while
that will power continuous growth for the technology engineered to enable back- the wafer stage is in motion—an
semiconductor industry. Over the years, end imperatives. architecture also known as “parallel
the packaging industry has relentlessly We have developed Multicolumn writing on the fly.” This allows MEBL
transitioned to enabling technologies. Electron-Beam Litho (MEBL) systems that to yield 20x to 100x higher productivity
First with flip-chip, then wafer-level perform maskless patterning to meet current than single-beam lithography systems
packaging, and now 2.5D and 3D and projected back-end requirements, as found in research labs. Incidentally,
packaging technologies. Today, however, discussed in the sections below. in e-beam mask-making (an adjacent
these technologies are being stretched Edge computing. Edge computing market of MEBL), single-beam writing
to their limits by certain constraints of eliminates the bottleneck of data- systems are being replaced by multi-
conventional back-end lithography tools. transfer between the edge device and beam writing systems for the same
Take edge computing, for example. Already data center. MEBL’s fine-resolution and reason – higher productivity.
on a growth trajectory, this application direct-write capabilities enable higher Large depth of focus (DoF). In
requires large storage and high I/O to meet interconnectivity and higher bandwidth advanced systems-in-package, the
aggressive new demands in data analysis, between chiplets. Dense interconnects substrate may be stressed and warped
inference, and decision making at the edge and I/O can be integrated without the by processes such as through-silicon via
of the network. The new requirements are need for large, power-hungry SERDES (TSV) or bonding, resulting in an uneven
driving new technical imperatives for back- circuits presently required for high- surface. This poses challenges to optical
end lithography tools. bandwidth communication between lithography, which is known for its
The rising prominence of advanced chips. All this helps speed in-package shallow DoF. The problem intensifies at
p a ck a g i n g w a s n o t e d by T SMC data analysis, inference, and decision finer resolutions because optics capable
chairman, Mark Liu, as he recently making, thereby optimizing overall of higher resolution have correspondingly
remarked that, “Demand for advanced smart computing of edge devices. smaller DoF. By using a 100x larger DoF
packaging far exceeds the current La r g e i n t er p o s er s . To d a y ’s than advanced optical systems [4], we
production capacity [1].” Liu further interposers are limited to the size of one were able to overcome this limitation at
noted that the company is, “accelerating optical field of view, or a few optical finer resolutions. This DoF advantage
the increase in production capacity,” to reticle fields, stitched together. In enables patterning of high-resolution
match demand for advanced packaging contrast, MEBL’s auto-stitch capability interconnects with relaxed requirements
and, “support the next generation of enables very large-scale interposers, for substrate flatness, bow, and warpage.
HPC, AI, mobile applications…to help spanning up to full-wafer. Such large It helps to overcome pat ter n i ng
customers achieve product success and interposers enable a unique flexibility to challenges associated with non-f lat
seize market opportunities [1].” integrate additional powerful processors surfaces in advanced packaging.
Conventional flip-chip packaging for HPC, graphics processing units Rapid cycles of learning. New
(still used today) has a minimum pitch of (GPUs), and AI engines. Furthermore, applications have ever-increasing
about 150µm and advanced microbumps MEBL is capable of patterning fine- requirements for system integration
have pushed minimum pitches to below interconnect pitches with more than and performance, and, “Increasing
50µm, yet there remains a critical 10 times higher resolution. This finer complexity continues to create new
bottleneck. To overcome the limitations, resolution creates much greater chip- challenges for package design,” as noted
s ome “ big t e ch” c om p a n ie s a r e to-chip bandwidth and reduces the in [5]. Cycles of learning are crucial to
employing in-house custom processors, SERDES overhead requirements. successful development of new systems-
accelerators, and networking silicon. High productivity. EBL has been in-package devices. Our system enables
But it’s clear that next-gen devices valued for decades as an enabling rapid testing of early concepts by writing
will inevitably need more chiplets and tool for research and pilot purposes. layouts directly onto substrates with no

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