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Semiconductor test: staying ahead of nanodevices
By Tucker Davis, Brian Brecht [Teradyne]
I n the semiconductor fabrication
process, engineers continue
to innovate, enabling smaller
transistors and higher density circuits.
The transition to FinFETs allowed 7nm
and 5nm processes to realize circuits
of amazing density, and the progress
of 3nm and gate-all-around (GAA)
transistors provides a clear path for
future advancement of digital circuit cost
reduction and performance improvement.
As higher transistor counts lead to
devices that are larger and more complex,
there is increased pressure to achieve
better test throughput and yields to
maintain manufacturing cost efficiency.
Here, we will explore how innovations to
the signal and power delivery architectures
will allow semiconductor manufacturers Figure 1: 42 years of microprocessor trend data. SOURCE: [1]
to achieve better throughput and yield to
manage overall costs. turn our focus to how these devices will increases test vectors and test times,
be designed and tested to keep up with and creates a higher need for repair and
Processing demand: no sign of this growth in complexity. trim. This drives new test challenges in
slowing terms of signal delivery to the device
The past two years have witnessed From FinFET to GAA under test (DUT), which are summarized
u n p r e c e d e n t e d g r o w t h i n t h e Looking forward, GAA is shaping up in Table 1. This new set of challenges
semiconductor industry driven by to be the enabler for transistor count to will be disruptive to many traditional
advances in artificial intelligence (AI), continue increasing, ensuring complexity test strategies, but a new generation of
natural language processing, automated continues its exponential growth and with automatic test equipment (ATE) systems
vehicles, and aug mented /vi r t ual it, an expansion of test requirements. The are available to meet these requirements.
reality. All of these applications require new nanowire or nanosheet structures Modern automatic test equipment
enormous computational processing and forming GAA allow more transistors in has extremely dense instruments to
communications bandwidth to make sense each device, but also bring new defects, measure and provide thousands of
of the proliferation of sensing and real- in addition to complexity. At a high level, high-performance signals and power
world interfaces, which depend heavily GAA boosts transistor density, which supplies to a wide variety of devices
on advancements in semiconductors.
We’ve witnessed the results as trends
in processors move to the forefront of
semiconductor processing, adding new AI
cores and increasing quality standards at
very high volume while controlling costs.
F i g u r e 1 [1] i l l u s t r a t e s t h e
historical growth of transistors per
microprocessor, demonstrating that
the pace of processing demand, as
expressed by device complexity, has
continued on an exponential growth
path for 50 years. We see no signs of
the demand for more processing power
slowing. With transistor counts reaching
the 100s of billions per die, we must
Table 1: Summary of test challenges for GAA devices.
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