Page 23 - Chip Scale Review_May June_2022-digital

Finally, the incoming signal is captured by a power densities. This predicament comes Endnotes
flop. What is interesting here is the simplicity along at the same time as Moore’s Law is 1. AMD 3D Chiplet Technology
and the compactness of the fully-digital IO doing less and less for power. Managing and -Competition 3D architecture picture
circuitry, which contributes to the power mitigating thermal issues is going to be an from SystemPlus. Intel Core i5-
efficiency and low latency of this hybrid- interesting and exciting area for innovation, L16G7: the first utilization of Intel’s
bonded 3D interface. So how does this along with power delivery solutions and high Foveros Technology with Package-on-
translate to performance? In a desktop gaming current densities across multiple dice means Package configuration in a consumer
system, AMD 3D V-Cache™ delivered on a 3D power grid, among other things. All product.. https://www.systemplus.fr/
average 15% faster gaming performance our tricks of integrated regulators and power reverse-costing-reports/intel-foveros-
when compared with its non stacked Ryzen™ gating will need to be deployed to support the 3d-packaging-technology/
counterpart. This 15% is truly a generational power demands of all the layers in the design. 2. MLNX-001R: EDA RTL Simulation
leap in performance, which in the past has Silicon and package are merging with this comparison based on AMD internal
been enabled only by silicon node transitions. architecture. Enabling the right design tools testing completed on 9/20/2021
Milan-X server implementation of the that can seamlessly move from system to measuring the average time to
AMD V-Cache™ architecture enables three package to C4 to 3D interface, to truly deliver complete a test case simulation.
times the L3 cache compared to standard the best-in-class DTCO, is critical. Comparing: 1x 16C 3rd Gen EPYC
Milan processors. This additional L3 cache Finally, as mentioned at the outset, CPU with AMD 3D V-Cache
relieves memory bandwidth pressure and performance is delivered at the system level, Technology versus 1x 16C AMD
reduces latency –that in turn dramatically and these heterogeneous modular SoCs will EPYC™ 73F3 on the same AMD
speeds up application performance. need to be connected with the right software “Daytona” reference platform. Results
to deliver system-level performance where may vary based on factors including
3D stacking: future and challenges an increasing amount of differentiation can silicon version, hardware and software
3D cache stacking over CPU cores is just be delivered. configuration and driver versions.
the beginning of the 3D journey (Figure 10). 3. MLNX-021R: AMD internal testing
The future of 3D stacking is a function of Summary as of 09/27/2021 on 2x 64C 3rd Gen
TSV pitch and can spawn many architectural We are truly at a new era of computing. EPYC with AMD 3D V-Cache
innovations including IP-on-IP stacking, Design and innovation must take a step up. (Milan-X) compared to 2x 64C AMD
macro-on-macro stacking, IP folding/ The new paradigms will combine traditional 3rd Gen EPYC 7763 CPUs using
splitting, as well as circuit-level slicing 3D CPU compute engines heterogeneously with cumulative average of each of the
stacking technology progression. These accelerators, using continuously evolving and following benchmark’s maximum test
innovations, along with other advanced improving package technology to enable levels result score: ANSYS® Fluent 2021.1,
®
packaging techniques, will enable beyond- of integration that today are at the board level. ANSYS CFX® 2021.R2, and Altair
®
Moore’s-Law scaling this decade and enable In the future, they will be at the integrated Radioss 2021. Results may vary.
complex heterogeneous integration schemes modular silicon level. System architectures, 4. MLN-075A: Altair™ Radioss™
not possible even with monolithic designs. previously only in massive supercomputers, comparison based on AMD internal
There are multiple challenges to enable 3D are now coming to the masses. It will be an testing as of 09/27/2021 measuring
chiplet architectures. All these chiplets need incredibly exciting next era of computing the time to run the neon, t10m, and
to be tested thoroughly before assembly or innovation driven by advanced packaging and venbatt test case simulations using
we throw away the entire expensive module. I look forward to the opportunities ahead! a server with 2x AMD EPYC 75F3
Stacking encounters challenges with higher

Figure 11: Schematic of 3D AMD V-Cache™ power delivery.

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