Page 44 - Chip Scale Review_January February_2022-digital
P. 44

MSL level 4 and TCT 1000 cycle TCT
                                                                              electrical test. Therefore, the 2.2D
                                                                              structure shows good potential for a
                                                                              heterogeneous integration substrate for
                                                                              both mid-end and high-end applications.
                                                                              Furthermore, we also disclosed that
                                                                              the 2.2D integrated substrate solution
                                                                              can be used in a 5/6G AiP structure,
                                                                              as a substitute in a current advanced
                                                                              ABF substrate, and in localized high-
                                                                              density bridges.

                                                                              Acknowledgment
                                                                                This article is based on materials
                                                                              originally presented at the 2021 IEEE 71st
                                                                              Electronic Components and Technology
                                                                              Conference (ECTC), June 2021.

                                                                              References
                                                                                1. D. C. Hu, E. Hao Chen, J. ChangBing
                                                                                  Lee, C. P. Sun, C. C. Hsu, “2.2D die-
                                                                                  last integrated substrate for high-
                                                                                  performance applications,” ECTC
                                                                                  2021.
                                                                                2. M. Swami nathan, K.  J. Han,
                                                                                  Design and Modeling for 3D ICs
                                                                                  and Interposers, World Scientific
                                                                                  Publishing Co. Pte. Ltd. 2014.
                                                                                3. D. C. Hu, “An innovative system
                                                                                  i nt eg r a t io n i nt er c o n n ec t io n
                                                                                  technology beyond BEOL,” IEEE
                                                                                  Inter. Interconnection Conf., Santa
                                                                                  Clara, U.S.A., 2018.
                                                                                4. D. C. Hu, J. Ho, “Methods to reduce
                                                                                  the hierarchy of interconnections in
                                                                                  electronic system,” Proc. of IMAPS
                                                                                  2020.
                                                                                5. W. H . Ya ng , R . Y. C h a ng ,
                                                                                  “Numerical simulation of mold
                                                            P                     fill in injection molding using a
                                                              RoHS
                                                                                  three-dimensional finite volume
                                                                                  approach,” Inter. Jour. for Numerical
                                                                                  Methods in Fluids, vol. 37, 2001.












                       Biography
                         Dyi-Chung Hu is CEO of SiPlus Co., Hsinchu, Taiwan, ROC. He is the founding member of a number of
                       high-tech companies including SiPlus Co., Raytek Semiconductor Co., Hannstar Display, and E-ink Co. He
                       was a SVP of R&D at Unimicron Technology Co. and was the founding chairman of the SEMICON Taiwan
                       Packaging Committee. He earned a PhD from MIT in Material Science and Engineering. Email hu@si2plus.
                       com




        42
        42   Chip Scale Review   January  •  February  •  2022   [ChipScaleReview.com]
   39   40   41   42   43   44   45   46   47   48   49