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TECHNOLOGY TRENDS
A paradigm shift in simulation techniques of
semiconductor test sockets
By Kevin DeFord, Khaled Elmadbouly, Jiachun (Frank) Zhou, Robert Friedt [Smiths Interconnect]
W
i t h t h e r i s e of t h e optimum signal/return pin layout (e.g., performance of the socket that can be
Internet of Everything signal with surrounding returns) as expected. As the signal/return pattern
(IoT), 5G, ar tif icial
i nt e l l i ge n c e ( A I ) shown in Figure 1. Socket test and changes in the socket, the standard
characterization are usually done in the
specification data that pertains to the RF
and augmented reality (AR), high- design validation stage of development performance is no longer relevant as the
keep pace. Performance specifications and socket structure, but do not include return layout of the customer’s device.
bandwidth changes, depending on the
with test coupons that represent the pin
performance test socket technology must
It i s g o o d p r a c t i c e t o d e s ig n
any of the parasitic effects caused by the
for test sockets published by suppliers
PCB and package alignment features of
symmetrical return paths around the
should only be used as a general
guideline in selecting the product family
for a test application. Once a socket the socket. The measurement produces high-speed lanes of the customer
S parameters of the entire test setup
device so the PCB and test socket can
technology is chosen based on the (Fixture A – device under test [DUT] – be designed to provide impedance-
general specification, suppliers should Fixture B). The test socket is then de- controlled differential pairs and guard
provide a more representative simulation embedded and gated in order to provide neighboring lanes against cross talk,
of the socket based on the customer’s basic performance data, such as the but real estate constraints don’t always
package layout with a focus on the high- -1dB insertion loss (IL), -10dB return allow chip designers to follow these
speed areas of the device. Typically, loss (RL), loop inductance (L), and design rules. Socket designers turn
simulations focus on the socket in mutual capacitance (Cm) IL, without to simulation tools such as HFSS to
a vacuum and do not consider other the effects of test fixtures and/or PCBs. determine the performance of these
features such as the printed circuit board Signal integrity performance data shown complex layouts because it is hardly
(PCB) pad, vias or the ball grid array in the product collateral regarding feasible to measure every instance of
(BGA) ball. As data rates and bandwidth the test sockets and contacts usually a customer’s layout due to package
continue to increase, a paradigm shift comes from measurements using this to package variability. It is equally
is emerging in the industry that is methodology. This information can then important that these simulation tools
driving socket suppliers to provide more be used by the customer to understand are calibrated through correlation
detailed simulations, which include the the basic performance of the socket and to measured data to ensure there is
device package and PCB interfaces in pin in an ideal condition in order to help confidence in the result that drives the
the analysis because of their impact on identify which socket family to use for a final decision. Suppliers traditionally
final socket performance in the system. given application. ignored BGA and PCB pad during
Most socket suppliers publish socket Once the buyer chooses the socket simulation because they do not have
characterization data based on an technology based on initial performance, control over the design of those features.
they can move into the next phase, Once the layout is established, and
which requires a detailed pin-out map the simulation completed, the IL, RL
of their device for simulation and and any cross talk effects are plotted
and used to determine if the design is
mechanical socket design. The pin-out
map provides a detailed layout of the suitable for the application. In some
signal, return and power pins as shown cases, the S-parameter files are provided
in Figure 2, which will later determine to the customer for Spice simulation at
the worst-case radio frequency (RF) the system level, but even at this level
of analysis, they do not capture the
complete system performance due to the
parasitic effects caused by the BGA and
PCB pad and via.
As we shift our focus from simulating
test socket performance in a vacuum
to include the parasitic effects that
PCB pads and the device present to
Figure 1: Example of an optimum signal/return the socket, customers will need to
, ,
, , pin layout. Figure 2: Example of a pin-out map.
Chip Scale Review September • October • 2020 [ChipScaleReview.com] 5 5
