Page 9 - Chip Scale Review_January-February_2024-digital

EXECUTIVE VIEWPOINT

Backside power delivery: The new frontier

for wafer bonding

By Paul Lindner [EV Group]

3 D integration stands as a of the wafer, leaving only signals to be the backside of the wafer using through-

silicon alignment lithography. These nano
pivotal technology in advanced
transmitted through frontside interconnects.
packaging and heterogeneous
BSPDN will be implemented in nodes below
hundred nanometers of silicon, end at the
integration—it facilitates The consensus within the industry is that TSVs, which are etched through several
performance scaling at the system level. 2nm, making it the industry standard in the tip of the BPRs. The process concludes with
While the evolution of packaging has upcoming advanced nodes. This transition the implementation of one or more backside
introduced 3D integration, progressing from is expected to commence in 2024, initially metal layers that electrically connect the
systems in package to stacked integrated in client compute and server applications. backside of the wafer to the BPRs on the
circuits (ICs) and 3D systems on chip, the frontside via the nano TSVs.
industry is currently witnessing another BSPDN manufacturing steps
significant turning point: backside power The integration of BSPDN offers different Wafer bonding co-integration with
delivery networks (BSPDN). approaches, each with unique advantages. In lithography processes
In the traditional scaling approach, both the first method, the logic cells have a buried Achieving low-distortion wafer-to-wafer
signal and power distribution coexist on power rail (BPR) to which the BSPDN is bonding is critical to enabling BSPDN.
the frontside of the wafer. However, the connected via a nano through-silicon via Because nano TSV contacting of BPRs or
growing demand for power, particularly (TSV). The second approach leaves the later versions of BSPDN requires sub-10nm
in power distribution, is increasingly power rail but instead uses a power via to overlay accuracy to the buried frontside
constraining the ability to achieve scalable transfer power directly from the BSPDN to structures, there must be compensation by
solutions. Efficient transistor scaling, the cell or transistor contact. Although this the lithography equipment for any incoming
crucial for achieving higher transistor method is more complicated, it improves distortion from frontside processing and
density, necessitates a proportional scaling power efficiency and allows for better cell wafer bonding. This is accomplished
of the power distribution network. This, area scaling. The third approach involves a through the co-optimization of wafer
however, encounters significant IR drop direct connection of the power supply from bonding and lithography.
challenges, leading to detrimental transistor the BSPDN to the source and drain contacts It is notewor t hy t hat for most
performance. Additionally, the interconnect of the individual transistors. applications, one of the wafers in the
design for signal and power is becoming In the first BSPDN implementation, bonded stack undergoes thinning to a scale
highly interdependent, constituting a BPRs are created during the front-end of several micrometers for subsequent
substantial portion (at least 20%) of the fabrication of the device. BPRs are defined processing. This thinning process induces
routing processes for power delivery. after a shallow trench isolation, which a relaxation in the bonded stack, aligning
Moreover, power density experiences a typically has a width of ~30nm and a pitch it closely with the original shape of the
rapid increase with scaling to the next node. of ~100nm. The metal is then recessed thicker wafer. Several strategies can be
The industry consensus is to decouple and covered with a dielectric, followed by proposed for lithography-based bonding
signal and power by implementing BSPDN. processing of the IC on the wafer frontside, overlay and distortion control. One such
This involves segregating the signal with a copper metallization back-end-of- strategy involves the bonding of a patterned
network on the frontside of the wafer line (BEOL) signal network completing the wafer to an unpatterned counterpart. In
and utilizing wafer-to-wafer bonding to front-side processing. such instances, concerns regarding overlay
efficiently access the transistor backside In the next step, the wafer with the between the wafers are mitigated because
for power distribution and management. devices and BPRs is flipped, with the active one of the wafers remains blank. However,
The key advantages include wider power frontside bonded to a blanket carrier wafer. the impact of bonding-induced distortion
lines with reduced IR drop, a more uniform This bonding is achieved by dielectric assumes prominence, especially considering
voltage distribution, and, most significantly, fusion bonding at room temperature, that, post-bonding, the patterned wafer is
more design space, thereby enabling further followed by a post-bond anneal. The typically thinned for continued processing
scaling of the standard cell height. backside of the first wafer is then thinned in with lithography from the backside of
BSPDN eliminates the need to share a sequential process of backside grinding, the device wafer. Consequently, any
interconnect resources between signal chemical mechanical polishing (CMP), and bonding-related distortion for which
and power lines on the wafer frontside. dry and wet etching steps. there is no compensation by a lithography
As implied by its name, backside power After depositing a passivation layer on scanner, significantly contributes to the
delivery relocates power to the back the backside, nano TSVs are patterned from overall overlay.

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