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minimum gap height of 100µm can d e f e c t m i n d s e t f o r a u t o m o t i v e applications post-SMT. Taking a holistic
be achieved between the LSC and dev ice s re qu i re s a f u nd a me nt al approach in studying both package- and
PCB ensuring a robust process free of understanding of assembly process board-level effects in tandem provides
continuity issues. variation and conditions, component high confidence for qualification, high-
I n a dd it ion , pr ior to t he SM T tolerances, materials, and chip-to- volume manufacturing (HVM), and
process of FCBGA to PCB, a multiple package interaction, to name a few. reliability in the field.
assembly lot investigation of the Meticulous inspection using in-line
gap height bet ween the LSC and optical inspection tools coupled with References
the collapsed BGA solder ball was destr uctive package constr uction AEC-Q200 specification, “Stress test
conducted after the FCBGA assembly a nalysis a re key be nch ma rk s t o qualification for passive components,”
process. With the target criteria of understand process margin. Outputs like Rev. D, June 1, 2010.
minimum gap height greater or equal solder thickness between the flip-chip Y. Min, et. al, “Embedded capacitors
to 130µm, all parts demonstrated a substrate and LSC, LSC thickness, and in the next-generation processor,” 2013
high process margin with Cpk values gap height between LSC and collapsed Electronic Comp. and Tech. Conf.
>1.67 in alignment with automotive BGA ball, are prerequisites to establish (ECTC).
physical dimension requirements. robust clearance between low-profile
Ultimately, ad her ing to a zero LSCs and the PCB for automotive

Biographies
Jaimal Williamson is a Packaging Engineer and Senior Member Technical Staff within Texas Instruments’
Worldwide Semiconductor Packaging group, Dallas, TX. His focal areas as a lead technologist include flip-chip
platform development, qualification, and productization to support multiple automotive, industrial, aerospace,
and defense applications. He received a BS in Chemistry from Grambling State U. and a MS in Polymers (via
School of Materials Science and Engineering) from Georgia Institute of Technology; email: jaimal@ti.com
David Chin is a Packaging Engineer within Texas Instruments Worldwide Semiconductor Packaging group in
Santa Clara, California. His areas of focus include: substrate-based module development, package qualification,
board-level reliability and failure analysis, providing PCB land patterns and stencils for all TI packages, and customer adoption
and surface mount support. He received a BSEE from U. of Missouri.

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