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Volume 26, Number 1
January • February 2022
The Future of Semiconductor Packaging
FEATURE ARTICLES (continued)
STAFF
Kim Newman 21 Bridges for chiplet design and heterogeneous
Publisher
knewman@chipscalereview.com integration packaging
By John H. Lau
Lawrence Michaels [Unimicron Technology Corporation]
Managing Director/Editor
lmichaels@chipscalereview.com
Debra Vogler
Senior Technical Editor 30 Managing trade-offs in the chiplet era
dvogler@chipscalereview.com By Rob Munoz
[Intel]
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By Dyi-Chung Hu
[SiPlus Co.]
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Lawrence Michaels
lmichaels@chipscalereview.com
Copyright © 2021 Haley Publishing Inc. 43 Heterogeneous integration for AI applications:
Chip Scale Review (ISSN 1526-1344) is a registered trademark of
Haley Publishing Inc. All rights reserved. status and future needs (part 1)
By Madhavan Swaminathan, Siddharth Ravichandran
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Chip Scale Review, (ISSN 1526-1344), is published six times a
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POSTMASTER: Send address changes to Chip Scale Review magazine 49 FOWLP and Si-interposer for high-speed
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