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Summary References uploads/2018/08/MS-FDSOI9.1818-
To summarize, a chiplet approach has 1. G. E. Moore, “Cramming more cr.pdf
tremendous potential to reduce portfolio compone nt s ont o i nt eg r at e d 11. As quoted in Mark Lapedus,
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Acknowledgments 2021.
The perspective I have shared is based 6. [6] JESD235D: High Bandwidth
on the work of Intel’s internal Chiplet Work Memory (HBM) DRAM, JEDEC,
Group. I especially want to thank Dave Mar. 2021, https://www.jedec.org/
Kehlet, Tanay Karnik, Ramune Nagisetty, standards-documents/docs/jesd235a
Peter Onufryk, and other collaborators in 7. H e ter o g e n e o u s I n te g r a t i o n
this effort over the last 5+ years. Roa d m ap, I EEE Ele ct ron ics
Packaging Soc., https://eps.ieee.
Legal disclaimer org/technology/heterogeneous-
Intel, the Intel logo, and other Intel integration-roadmap.html
marks are trademarks of Intel Corporation 8. R. Munoz, “Scaling the Chiplet
or its subsidiaries. Intel technologies Adoption Wall,” MEPTEC Report,
features and benefits depend on system Fall 2021, p. 14-18, https://issuu.
configuration and may require enabled com/mepcom/docs/meptec_report_
hardware, software or service activation. fall_2021
Performance varies depending on system 9. L i t ho g r a ph y 20 21 u p d a t e ,
configuration. I n t e r n at i on a l R o a d m a p f or
Statements in this document that Devices and Systems, IEEE, 2021,
refer to future plans or expectations https://irds.ieee.org/images/files/
a re for wa rd-look i ng st atements. pdf/2021/2021IRDS_Litho.pdf
These statements are based on current 10. “FinFET and FD SOI: Market
expectations and actual results may and Cost Analysis,” International
differ materially from those expressed or Business Strategies, Sept. 18, 2018,
implied in such statements. http://soiconsortium.eu/wp-content/

Biography
Rob Munoz is a Principal Engineer in Intel’s Design and Engineering group located in Austin, TX. His day
job is architecture for custom/semi-custom/standard products targeted at wireless infrastructure. He also co-
leads the cross-Intel Chiplet Working Group. He has been with Intel since November 2014, joining as part
of Intel’s acquisition of LSI/Avago’s networking business. He started his career at Bell Labs, has an MS in
Computer Science from UT Austin, and currently has 15 granted patents. Email robert.munoz@intel.com

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