Industry News - 2017

August 2017


MRSI Systems Launches High Speed Die Bonder for Photonics High Volume Manufacturing

North Billerica, MA, USA, August 14, 2017 - MRSI Systems, a leading manufacturer of fully automated, ultra-precision, high speed die bonding and epoxy dispensing systems, is launching a new High Speed Die Bonder, MRSI-HVM3, to support our photonics customers’ high volume manufacturing requirements. The MRSI-HVM3 is in full production and we are shipping to customers worldwide.

Scaling Imperatives
Our customers need to scale up manufacturing to unprecedented levels for advanced applications such as data center, telecommunication upgrades to 100G+, 5G wireless, IoT, and advanced optical sensors. Today, high volume manufacturing of photonic, sensor, and semiconductor devices demands a die bonding system that can deliver industry leading speed without sacrificing high precision and superior flexibility. Our new MRSI-HVM3, a high speed, flexible, 3 micron die bonder, has been built to address this challenge. This new system leverages a well-defined set of MRSI’s core competencies, built up over 30 years, in the areas of system design, software development, machine vision, motion control, industrial automation, and process solutions.

Customer Outcomes
As Dr. Yi Qian, Vice President of Product Management, states, “The new MRSI-HVM3 incorporates the latest hardware and software innovations. Equipped with ultrafast-ramp eutectic stations, it deploys multiple levels of parallel processing utilizing dual gantries, dual heads, dual bonding stages, and “on-the-fly” tool changes. Used across all products, MRSI’s platform software makes it easy for users to change process settings on their own for new parts, new processes, and new products. These features provide our customers with best-in-class throughput for capacity expansion; high accuracy for high-density packaging; and unmatched flexibility for multi-chip multi-process production in one machine. Ultimately the system will generate great ROIs for customers. The MRSI-HVM3 high speed die bonder supports many applications including chip-on-carrier (CoC), chip-on-submount (CoS), and chip-on-baseplate or board (CoB).” “MRSI Systems has been serving optoelectronic and microelectronic customers for the past thirty-three years and understands their requirement to scale efficiently in today’s fast paced marketplace. MRSI is pleased to meet these needs with the launch of our new high speed die bonder for high volume manufacturing of photonics packaging,” said Mr. Michael Chalsen, President, MRSI Systems.

Private Demonstrations at CIOE
MRSI Systems is exhibiting at CIOE with our Chinese Representative CYCAD Century Science and Technology (Booth #1C66) in Shenzhen, September 6-9, 2017. There will be private demonstrations of the MRSI-HVM3 performing CoC eutectic and epoxy bonding. Please reach out to your MRSI contact to ensure you have an opportunity to see the capabilities of this exciting new product.

For more information visit: www.mrsisystems.com.


Nanusens solves the problem of stiction in MEMS inertial sensors by going smaller and creating nano-sensors in standard CMOS

Barcelona, Spain - August 3, 2017 - Nanusens has announced that its CMOS nano-sensor technology has been successfully used to solve the problem of stiction in MEMS inertial sensors, which is a major source of failure for this type of sensor.

"Our first silicon nano-sensor samples from GLOBALFOUNDRIES exceeded our expectations showing outstanding resilience to stiction, with the devices going through more than 10,000 switching cycles, each equivalent to more than 1000G shocks," explained Nanusens' CEO, Dr Josep Montanyà i Silvestre. "And the sensitivity is an order of magnitude above what is needed for a motion sensor in most applications."

The problem of stiction in MEMS is caused by attractive forces that occur on microscopic levels such as Van der Waals and Casimir. These are surface area dependant and not mass dependant. In an inertial sensor design, there is a proof mass connected to a spring. This mass moves when there is an acceleration and the movement is detected by the mass acting as one electrode and the change in capacitance is measured relative to a second fixed electrode. However, if there is a large movement such as from a shock or collision, the mass goes beyond the normal range of travelling and touches a surface enclosing the sensor where it 'sticks' due to the attractive forces and stops working. This can be countered by having stronger springs but this reduces the sensitivity of the sensor. A solution to increase the sensitivity could be to increase the mass but this results in a greater surface area for the mass and so, unfortunately, more attractive forces.

The approach used by Nanusens is to reduce the sensor design by an order of magnitude from Micro ElectroMechanical Systems (MEMS) with linear feature sizes of 1-2um to Nano ElectroMechanical Systems (NEMS) where the features are 0.3um. This reduces the attractive forces significantly as the surface area reduction is in two dimensions, i.e. almost two orders of magnitude reduction. Reducing the proof mass could result in decreased sensitivity except this is offset by reducing the gap between it and the fixed electrode. The size reduction also means that the energy stored on the proof mass when it hits the surface in case of a shock, it is much less and the travelling gap is also small. A shock with less energy is also easier to detach.

"Therefore, by reducing all the dimensions of the device, we keep the sensitivity and we increase the reliability," added Dr Montanyà. "In fact, we have such a gain in reliability, that we can increase sensitivity and still have a very reliable device."

The new nano-sensors are made using standard CMOS processes and mask techniques. The Inter Metal Dielectric (IMD) is etched away through the pad openings in the passivation layer using vapour HF (vHF) to create the nano-sensor structures. The holes are then sealed and the chip packaged as necessary. As only standard CMOS processes are used, and the sensors can be directly integrated with active circuitry as required, the sensors can potentially have high yields similar to CMOS devices.

Nanusens has perfected this CMOS nano-sensor technology over the past year based on developments that the key staff had done when working at Baolab Microsystems, which closed in 2014. It was the success of this previous work that has enabled Nanusens to partner with GLOBALFOUNDRIES (GF).

Rajesh Nair, vice president of product management at GF, commented, "We have built a strong relationship with Nanusens and we look forward to advance this new generation of sensor designs using our standard 0.18um processes."

Dr Montanyà concluded, "Nanusens decided to partner with GF to develop its nano-sensors due to the outstanding technical expertise and quality of service received from their teams, together with such a large variety of CMOS nodes where we plan to move some of the devices in the future including many RF options. In addition to this, producing our nano-sensors at GF, with their huge volume capacities that keep growing due to their continuous investment in their global footprint ensures that Nanusens will have all the required production capacity that it will need in the future, and that there will never be a shortage in supplying our products to the customers. This large volume capacity is key to serve the consumer market, where demand can fluctuate very quickly, and there can be unexpected peaks."

For additional information, contact Nigel Robson @ nigel@vortexpr.com


EV GROUP CELEBRATES 20 YEARS OF SUPPORTING MICRO- AND NANO-TECHNOLOGY DEVELOPMENT IN JAPAN

EVG Technology Day Event in Yokohama Highlights Process Solutions Supporting Internet of Things (IoT) Applications

St. Florian, Austria, August 2, 2017 - EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it is celebrating the 20th anniversary of its wholly owned subsidiary in Japan, EV Group Japan KK. Established in August 1997 in Yokohama, EV Group Japan has since expanded its presence to include offices in Fukuoka and a state-of-the-art applications lab in Yokohama for process and product demonstrations, as well as increased the number of employees in the country by nearly three-fold.

EV Group Japan K.K. headquarters at Yokohama Business Park

EV Group's wafer bonding and lithography solutions have played an important role in supporting the Japanese semiconductor market as it has evolved from leading-edge logic and memory manufacturing to include the production of advanced MEMS, image sensors, power devices, optical components and high-functional materials. For example, the company's GEMINI®FB fusion wafer bonders and EVG®40NT automated measurement systems are being utilized in Japan to support the manufacture of 3D-integrated CMOS image sensors. In addition, the EVG®850 and EVG®850LT automated production bonding systems for silicon-on-insulator (SOI) and direct wafer bonding are enabling substrate manufacturers in Japan to produce void-free, high-yielding SOI and engineered substrate wafers for low-power, high-switching-frequency and other enhanced-performance device applications.

As Japan gears up for the 2020 Tokyo Olympics, expectations are high that visitors will witness a wide variety of technology innovations at the 2020 games. Examples may include: driverless taxi service; electronic passes known as the Wonder Japan Pass for entry to both the stadium and spectators' hotels; smart streets with underground electrical lines that deploy street hubs for emergency information, Wi-Fi hotspots, and power outlets for pop-up businesses; and enhanced stadium security involving tens of thousands of fixed and mobile cameras and sensors. EVG's process equipment and solutions enable the manufacture of the electronic devices that would power these various Smart City developments.

"EV Group has an extensive history in Japan supporting local universities, research institutes and device manufacturers at the forefront of micro- and nano-electronics technology," stated Hermann Waltl, executive sales and customer support director at EV Group. "For the past 20 years, EVG Japan has achieved many important milestones, such as supporting the production of the world's first back-side illuminated sensors with our wafer bonding equipment. EVG is proud to play a role in helping our partners and customers in Japan continue to shape this region as a center of innovation in automotive technology, energy, displays, telecommunications and information management."

Coinciding with the 20th anniversary of EV Group Japan KK, EVG is hosting its annual EVG Technology Day event today in Yokohama. At this event, executives from EVG, TowerJazz Panasonic Semiconductor Co., SPP Technologies and ROHM Co., along with Dr. Masayoshi Esashi of the Tohoku University Micro System Integration Center, will present on the latest developments with EVG's process solutions in supporting the production of MEMS, image sensors and other devices that are driving IoT/smart applications. For more information, please visit:
www.evgroup.com/en/about/events/evgtechdayjapan17/.


Woodside Capital Partners and Yole Développement announce a joint venture agreement to expand their market research expertise

LYON, France – August 1, 2017: Woodside Capital Partners International LLC, a global, independent investment bank and Yole Développement SA (Yole) announce a joint venture. Yole will serve as a research partner for Woodside Capital’s M&A advisory practice, which provides strategic and financial advice to emerging growth companies in the technology sector.

Yole focuses on a number of the technology sectors within Woodside Capital’s electronics practice. Yole’s analysts are subject matter experts in MEMS and Sensors; Imaging; Advanced Packaging; Power Electronics; Solid-State Lighting; Displays; Photonics; Optoelectronics; Compound Semiconductors and Substrates; RF Electronics devices and technologies; and MedTech. Under the research partnership, Yole and Woodside Capital will jointly develop in-depth technology & market reports, which will benefit the client base of both companies.

“Synergies between Woodside Capital and Yole are just unique and impressive,” said Jean-Christophe Eloy, Yole’s President & CEO. “Together with Woodside Capital, the leader in research and M&A financial advising in various emerging growth tech industry sectors, we will be able to provide immediate value to both of our client basis.”
“Our collaboration with Yole will help us deliver the critical market and technology insights that our global M&A customers depend on” said Rudy Burger, Managing Partner at Woodside Capital Partners. “Yole will bring the extensive technical expertise and its relevant industry knowledge of its worldwide team of analysts to Woodside Capital’s industry leading research and advisory services.”

For additional information:
Sandrine Leroy
PR & Corporate Communications Manager - eMail: leroy@yole.fr


TechSearch International Analysis Examines FO-WLP Developments and Sensor Packaging Trends

Austin, TX - July 19, 2017 - Mobile devices, specifically smartphones, represent the single greatest volume driver for MEMS and other sensors today. Sensors found in these products include electronic compasses, motion sensors, barometers, microphones, and fingerprint sensors. Package types include land grid arrays (LGAs,), leadframe packages such QFNs, and wafer level packages (WLPs.). Apple is expected to account for 28 percent of the total smartphone sensor market as a result of increased sensor adoption. With the trend toward smart factories, industrial applications are also expected to account for increased sensor demand.

New FO-WLP versions are targeting high-performance applications including networking, data centers, and artificial intelligence. Fan-out on substrate versions such as ASE’s Fan-Out chip-on-Substrate (FOCoS), TSMC’s InFO_oS, and Amkor’s Silicon Wafer Integrated Fan-out Technology (SWIFT™) are being considered as a low-cost heterogeneous integration alternative to silicon interposers. FO-WLP on substrate fills the interconnect gap between lower-density FO-WLP and the highest density silicon Interposers.

The analysis is provided in the latest Advanced Packaging Update, an 84-page report with full references and an accompanying set of 46 PowerPoint slides. The report also provides results from TechSearch International’s annual survey on substrate design rules. The design rules include body size, core thickness, via and pad diameter, minimum bump pitch supported, and substrate finish.

For more information, contact TechSearch at tel: 512-372-8887 or visit www.techsearchinc.com.


Toshiba Memory Corporation Develops World's First 3D Flash Memory with TSV Technology

Achieves high speed data input and output, low power consumption, large capacity

July 11, 2017 - Tokyo, Japan --(BUSINESS WIRE)--Toshiba Memory Corporation, the world leader in memory solutions, today announced development of the world’s first[1] BiCS FLASH™ three-dimensional (3D) flash memory[2] utilizing Through Silicon Via (TSV)[3] technology with 3-bit-per-cell (triple-level cell, TLC) technology. Shipments of prototypes for development purposes started in June, and product samples are scheduled for release in the second half of 2017. The prototype of this groundbreaking device will be showcased at the 2017 Flash Memory Summit in Santa Clara, California, United States, from August 7-10.

The World's First 3D Flash Memory with TSV Technology (Photo: Business Wire)

Devices fabricated with TSV technology have vertical electrodes and vias that pass through silicon dies to provide connections, an architecture that realizes high speed data input and output while reducing power consumption. Real-world performance has been proven previously, with the introduction of Toshiba’s 2D NAND Flash memory [4].Combining a 48-layer 3D flash process and TSV technology has allowed Toshiba Memory Corporation to successfully increase product programming bandwidth while achieving low power consumption. The power efficiency[5] of a single package is approximately twice[6] that of the same generation BiCS FLASH™ memory fabricated with wire-bonding technology. TSV BiCS FLASH™ also enables a 1-terabyte (TB) device with a 16-die stacked architecture in a single package.

Toshiba Memory Corporation will commercialize BiCS FLASH™ with TSV technology to provide an ideal solution in respect for storage applications requiring low latency, high bandwidth and high IOPS[7]/Watt, including high-end enterprise SSDs.

General Specifications (Prototype)
Package Type NAND Dual x8 BGA-152 Storage Capacity 512 GB 1 TB Number of Stacks 8 16 External Dimension W 14 mm 14 mm D 18 mm 18 mm H 1.35 mm 1.85 mm Interface Toggle DDR Interface Max. Speed 1066Mbps

Notes:
[1] Source: Toshiba Memory Corporation, as of July 11, 2017.
[2] A structure stacking Flash memory cells vertically on a silicon substrate to realize significant density improvements over planar NAND Flash memory, where cells are formed on the silicon substrate.
[3] Through Silicon Via: the technology which has vertical electrodes and vias to pass through the silicon dies for connection in a single package.
[4] “Toshiba Develops World’s First 16-die Stacked NAND Flash Memory with TSV Technology”
http://toshiba.semicon-storage.com/ap-en/company/news/news-topics/2015/08/memory-20150806-1.html
[5] The rate of data transfer rate per power unit. (MB/s/W)
[6] Compared with Toshiba Memory Corporation’s current products.
[7] Input Output per Second: The number of data inputs and outputs for processing through an I/O port per second. A higher value represents better performance.

For additional information:
Toshiba Memory Corporation
semicon-NR-mailbox@ml.toshiba.co.jp


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