2018 Issues

November • December 2018; Volume 22, Number 6

Collective die-to-wafer bonding enables heterogeneous integration of dies from different sources through the use of fusion/hybrid, adhesive or thermocompression bonding by a die carrier. The photo shows a group of compound semiconductor dies after successful transfer to a 300mm silicon wafer for further processing.

Cover image courtesy of EV Group

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September • October 2018; Volume 22, Number 5

The ZEISS Xradia 520 Versa X-ray microscope (XRM) provides non-destructive package-level failure analysis and 3D volumetric and linear measurements on packaging structures with submicron resolution. The photo, taken inside the XRM chamber, shows a loaded sample being prepared for measurement just after placement by the robotic arm. The XRM system collects 2D projection images from the rotating sample, which is positioned between an X-ray source and detector, and then uses proprietary software to reconstruct 3D volume data that may be visualized and analyzed. Scintillator-coupled microscope objectives enable it to maintain resolution regardless of package size.

Cover image courtesy of Zeiss.

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July • August 2018; Volume 22, Number 4

Zuken’s CR-8000 PCB and package layout design tools enable multiple chips, packages and boards to be assembled, viewed and edited on one canvas in either 2D- or 3D-mode. The image shows a three-die stack on a silicon interposer that is wire bonded to a package and placed on a board. A simple click into any one of these components in a hierarchy tree switches edit context to the selected part, including its specific technology, rules and layer stack-up.

Cover image courtesy of Zuken USA Inc.

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May • June 2018; Volume 22, Number 3

Advanced packaging techniques like FOWLP demand mature lithography solutions for the challenging processes required to manufacture high-performance devices. The Veeco-Ultratech AP300®, which was used for the research in the featured article, has a variable numerical aperture lens that can be optimized to maximize depth of focus while maintaining higher resolution performance. It can process wafers with up to 7mm of warpage and is configurable with an optical system that provides a full wafer topography map to help optimize the focus position for each exposure.

Cover photo courtesy of Veeco Instruments Inc.

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March • April 2018; Volume 22, Number 2

The photo is a graphical representation of an intermediate step in the RDL-first fan-out process whereby the dies are placed on top of the redistribution layer (RDL) architecture before overmolding. Prior steps in the process include application of a release layer to the carrier, followed by addition of redistribution layers on top of the release layer. The RDL-first fan-out process offers distinctive advantages in terms of reduced known good die (KGD) loss, improved line/space density, etc.

Cover photo courtesy of Brewer Science Inc.

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January • February 2018; Volume 22, Number 1

A 300mm wafer and a 510 x 515mm panel are about to be electroplated for packaging. Electroplating at the panel scale is no longer a barrier for form factor adoption in packaging. Tokyo Electron has partnered with customers to develop cutting-edge processing equipment, such as the StratusTM P300 and P500 that can process the substrates shown to create fine packaging features at superior uniformities.

Cover photo courtesy of Tokyo Electron.

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