2016 Issues

November • December 2016; Volume 20, Number 6

The semiconductor and MEMS sensor industry is rapidly growing. Every day, new applications, next-generation materials, and state-of-the art information gathering sensors are being created. Each new device must be packaged and electrically connected to the outside world. A robust and reliable interconnect is critical to the success and function of every integrated circuit, sensor and device. Advanced technologies, new manufacturing technologies and novel materials come with unique challenges when it comes to making robust and reliable interconnects.

Cover image courtesy of SMART Microsystems Ltd.

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September • October 2016; Volume 20, Number 5

Thin wafer handling by temporarily bonding device wafers to a supporting carrier has been widely used for advanced packaging of high-efficiency and high-performance devices used in computing, networking, sensors and consumer electronics applications. Temporary bonding material is a significant factor in this process and has evolved substantially over the last decade to enable handling of extremely thin wafers in harsh environments during wafer processing.

Cover image courtesy of Brewer Science Inc.

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July • August 2016; Volume 20, Number 4

Eutectic bonding is an area of particular interest to photonics, microwave and RF electronics, because of the need for a clean,highly thermally efficient process, as well as for long-term reliability. Increasing demand for communications data and bandwidth accelerates the adaptation of full automation and the improvement of processes in advanced eutectic packaging for volume production.These advances result in high-precision, high-throughput, improved yield, and new products for the component and module manufacturers.

Photo courtesy of MRSI Systems

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May • June 2016; Volume 20, Number 3

A plasma etch module that provides high-rate, low non-uniformity Si via reveal etch is important to one of the final and critical steps in the 3D wafer stacking process flow (see cover article on p.45). Combining a high-throughput Si thinning process with high selectivity to the oxide liners delivers the smooth wafer surface needed for the subsequent steps to complete the 3D process flow.

Photo courtesy of SPTS Technologies

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March • April 2016; Volume 20, Number 2

In the thin chip foil package, ultra-thin dies are placed in a cavity of a film laminate, which results in a bendable fan-out chip package with the fragile IC securely embedded in the center layer. The capability to bend flat chip packages and mount them onto curved surfaces will enable new sensing applications in production environments, healthcare, robotics and potentially any aspect of our daily life.

Photo courtesy of Fraunhofer EMFT

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January • February 2016; Volume 20, Number 1

Chip-to-wafer stacking enabled by 3D integration has significant potential to improve device performance while reducing power consumption. There are many possibilities for collaboration between foundries and OSATs, specifically with ultraprecise stacking (<1μm). Leti‘s roadmap calls for developing fine pitch, from classical thermocompression stacking with copper pillar, to ultra-dense bonding using Cu-Cu technology. Ultra-precise C2W is a promising possibility for the next generation of 3D-ICs.

Photo courtesy of NANIUM and EV Group

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