2013 Issues

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November-December 2013; Volume 17, Number 6

The drive toward increasing parallelism in testing semiconductor devices raises new challenges for test sockets. The front cover shows an assembly of Centipede’s contactor cartridges configured to test an array of 40 Greenliant SATA drives at KYEC facilities in Chu Nan. During testing over a full range of temperatures, the contactor assembly is enclosed in a sealed mini-chamber to avoid condensation.

Cover image courtesy of KYEC


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September-October 2013; Volume 17, Number 5

The integration of different known good dies from different wafers, produced in different technologies and fulfilling different functions is best done by Fan-out Wafer Level Packaging technologies like eWLB. It enables the highest integration density, thinnest package, smallest die-to-die distance and shortest interconnections realized substrate-less by thin-film redistribution layer. The picture shows part of a reconstituted 300mm mold wafer with different dummy dies embedded.

Source: Nanium S.A.


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July-August 2013; Volume 17, Number 4

This photo demonstrates the wire bonding operation in the chip assembly manufacturing process. The machine attaches lead wires to the chip. It is commonly a constraining step in the assembly manufacturing process. Technologies such as Applied Materials' dispatching software determine what chips are best to process next in real time. This has proven to increase throughput at manufacturing bottleneck steps like wire bonding.

Photo courtesy of Applied Materials


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May-June 2013; Volume 17, Number 3

The cover photo shows Altera’s Stratix® IV 40- nm wafer and a close-up of a Stratix®V GT 28- nm die. Stratix® devices are high performance, high density FPGAs. The illustration, showing Amkor’s POSSUM™ packaging approach, depicts the FPGA flip chip mounted to the substrate with a thinned ASIC attached underneath. The two devices are assembled face-to-face through a 40µm array of Cu pillar micro-bumps. The ASIC is joined to the substrate through thicker Cu posts + solder microballs at a conventional solder bump pitch


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March-April 2013; Volume 17, Number 2

The EVG IQ Aligner® is a 1X full-field exposure system optimized for 2.5D interposers based on chip to-wafer integration. Thin film processing of a thin wafer on a carrier before and after chip-to-wafer stacking, as well as after over molding, are enabled by a number of features. The detailed process flow for a 2.5D interposer integration scheme is described in the cover story.

Photograph courtesy of EV Group Europe & Asia/Pacific GmbH


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January-February 2013; Volume 17, Number 1

The cover photo shows Bond Via Array™ (BVA™) PoP technology from Invensas. It enables 1000+ memory-logic IO utilizing free-standing wire structures in lieu of TSVs. The technology addresses the industry's need for increasing the performance of processor-memory interconnect as it transitions from single core to multi-core CPUs, while also handling the requirements of low-power computing and cloud computing. It can be used in applications such as 3D packaging, embedded packaging, and WLP.


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