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This edition’s cover dramatically depicts sand or silica (aka: silicon dioxide) as the raw material for transformation to a silicon wafer. This process is achieved through many steps including the Czochralski process and eventually results as this flip-chip ball grid array. During the manufacturing cycle a number of sequential processes occur to achieve this final step. In this edition of CSR we have assembled a rich set of in-depth articles that unravel a few areas of these complex transforming processes that range from TSV silicon interposers, wafer test/probing and the increasing adoption of copper wire bonding, the criticality of emphasis for design and test reliability and the significant challenges of ultra-low alpha emitting solder materials.
This edition’s cover features an inside view of SET’s FC300 Automated High Force Die / Flip Chip Bonder for automated handling of chips and substrates up to 100 mm from waffle packs. With ± 0.5 µm post bond accuracy and 20 µ radians leveling, the SET FC300 offers the latest evolutions in bonding techniques. The article “Flip Chip Die Bonding for 3D IC Integration”explores some of the new challenges, advantages, and options.
Photograph Courtesy: EV Group Europe & Asia/ Pacific GmbH. Thin wafer processing is a key enabling technology for TSVs and 3D interconnects. By adding only 2 process steps, temporary bonding and debonding, every existing fab can be upgraded for thin wafer handling capability. In the picture a process engineer in EV Group's application lab inspects a 50µm thin 300mm wafer on a film frame.
Photograph by Jeff Maloney: This edition's cover depicts a technician inspecting a wafer through a defect inspection system in a clean room envir onment. Chip Scale Review brings to readers The International Directory of Defect Inspection Systems which provides the most comprehensive listing of Acoustic, Optical & XRay Systems.
Photograph by Steve McAlister This edition's cover depicts a large wafer being displayed by a clean-room technician. These wafers substrates are the primary foundation for the microelectronic devices. This process starts at the semiconductor fabrication plants, John H. Lau's article (page 22) goes in-depth in “State-of-the-art and Trends in 3D Integration."
Tessera Wafer-Level Camera (WLC) technologies, including wafer-level optics and image sensor packaging, enable manufacturers to significantly advance the integration of miniaturized cameras in cell phones, personal computers, security cameras and other portable devices.
Cover Artwork courtesy of Design 2 Market.