Data centers (i.e., AI, machine learning, deep learning, computation run-off data center hardware) are driving next generation semiconductor packaging, especially 2.5D and 3D integrations. In particular, data centers are the primary target market for 3D DRAM, 3D NAND for SSDs, and 2.5D CPU/GPU/FPGA/SoCs, etc. These devices are the focus of all the large semiconductor companies for not only their current high-end product lines, but also those of the future.
Cover art courtesy: XPERI Corporation
Chip Scale Review and SMTA are pleased to announce the program for the 16th annual International Wafer-Level Packaging Conference (IWLPC). The conference will be heldOctober 22-24, 2019 at the DoubleTree by Hilton Hotel in San Jose, California USA.
The technical sessions on Tuesday and Wednesday are organized into three tracks: Wafer-Level Packaging, 3D Packaging, and Advanced Manufacturing and Test.The Wafer-Level Packaging (WLP) track features sessions on materials, reliability, metrology, processing, and new technology, such as Fan-Out WLP.
The 3D Packaging track features sessions on design, test, characterization, wafer bonding, chip stacking, and processing for Fan-Out. The Advanced Manufacturing track features sessions on process materials, equipment, inspection, and more.
Registration for IWLPC is now available online. Discounted rates are available for conference registration made on or before September 27, 2019.White Paper: System-level, post-layout electrical analysis for high-density advanced packaging