Andy received a PhD in physical chemistry from the U. of Nottingham, UK, and an MSc in colloid and interface science from the U. of Bristol, UK. He is an iMAPS fellow, and was the 2014 recipient of the William D. Ashman Achievement Award for leadership and technical contributions to the semiconductor packaging industry from iMAPS. He has over 25 years of experience in new product and process development and materials marketing in all areas of electronics manufacturing from wafer fabrication to semiconductor packaging and electronics assembly. Additionally, he holds patents in novel polymers, gas analysis, and solder paste formulation. He is formally trained in Six Sigma - Design of Experiments and is the author of Indium Corporation’s Semiconductor Assembly blog.
Rolf received his BS degree in mechanical engineering from the U. for Applied Science, Gießen, Germany, and an MS degree in physics from the U. of Gießen, Germany. He has 22 years of experience including joining the Fraunhofer IZM in 1994 where he is now the Deputy Director and head of the department of System Integration and Interconnection Technologies. He has held various leadership roles with IEEE CPMT including serving as president. In 2012, he became an IEEE Fellow, and in 2013, he received the CPMT David Feldman Award. He holds patents in 17 technology areas including: solder bump for flip-chip assembly and method of fabrication, flip-chip bonding with non-conductive adhesive, coating method for application of solder material to contact bumps using magnetization of contact bumps, etc.
Arun Gowda received his MS and PhD from Binghamton University, specializing in Electronics Packaging. Arun is a Six Sigma Black Belt and a TRIZ Level 3 Practitioner. He is also a visiting professor in the System Science and Industrial Engineering department at Binghamton University. Arun has over 12 years of experience in the development of advanced materials, structures, andassembly processes for the packaging of various semiconductor devices, MEMS, and sensors. Arun holds patents in novel packaging structures for power devices, MEMS and sensors, and new materials and structures for thermal management of electronics.
John received a PhD in Theoretical & Applied Mechanics from the U. of Illinois at Champagne-Urbana and three master degrees in North America. He is the author of more than 415 peer-reviewed papers and 17 textbooks on electrics and optoelectrics packaging. He has over 30 years experience in 3D IC integration, advanced MEMS packaging, reliability of 2D and 3D IC interconnects, flip chip & WLP, area-array packages, high-density PCB, SMT, COB, and lead-free materials, soldering, manufacturing and solder joint reliability. Additionally, he holds patents in novel flip chip, area array, solder ball mounting, TSV, and 3D IC integration technologies.
Leon received his BEng in thermal engineering from Tsing Hua U., a PhD from NUS U. of Singapore, and an MBA from the U. of Adelaide, Australia. Among his areas of specialization are: advanced packaging in TSV/TSI, Cu wire bonding, high power modules, thermal management, and smart phone design and development. A certified black belt in Motorola, he has over 6 patent applications in various areas of SMT, and semiconductor packaging design and testing. He is also a former member of the IEEE (Singapore) and has held various international technical paper review and selection committee positions.